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HA5340/883
June 1994
High Speed, Low Distortion, Precision Monolithic Sample and Hold Amplifier
Description
The HA-5340/883 combines the advantages of two sample/hold architectures to create a new generation of monolithic sample/ hold. High amplitude, high frequency signals can be sampled with very low distortion being introduced. The combination of exceptionally fast acquisition time and specified/characterized hold mode distortion is an industry first. Additionally, the AC performance is only minimally affected by additional hold capacitance. To achieve this level of performance, the benefits of an integrating output stage have been combined with the advantages of a buffered hold capacitor. To the user this translates to a front-end stage that has high bandwidth due to charging only a small capacitive load and an output stage with constant pedestal error which can be nulled out using the offset adjust pins. Since the performance penalty for additional hold capacitance is low, the designer can further minimize pedestal error and droop rate without sacrificing speed. Low distortion, fast acquisition, and low droop rate are the result, making the HA-5340/883 the obvious choice for high speed, high accuracy sampling systems.
Features
* This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. * Fast Acquisition Time (0.01%) . . . . . . . . . . . . . . . 900ns * Fast Hold Mode Settling Time (0.01%) . . . . . . . . . 300ns * Low Distortion (Hold Mode) . . . . . . . . . . . -72dBc (Typ) (VIN = 200kHz, Fs = 450kHz, 5VP-P) * Bandwidth Minimally Affected By External CH * Fully Differential Analog Inputs * Built-in 135pF Hold Capacitor * Pin Compatible with HA-5320
Applications
* High Bandwidth Precision Data Acquisition Systems * Inertial Navigation and Guidance Systems * Ultrasonics * SONAR * RADAR
Pinouts
HA-5340/883 (CERDIP) TOP VIEW
Ordering Information
PART NUMBER TEMPERATURE RANGE -55oC -55oC to to +125oC +125oC PACKAGE 14 Lead CerDIP 20 Lead Ceramic LCC
-INPUT 1 +INPUT 2 OFFSET ADJ 3 OFFSET ADJ 4 V- 5 SIG GND 6 OUTPUT 7
14 S/H CONTROL 13 SUPPLY GND 12 NC 11 EXTERNAL HOLD CAP 10 NC 9 V+ 8 NC
HA1-5340/883 HA4-5340/883
Functional Diagram
OFFSET ADJUST 3 4 CHOLD EXTERNAL (OPTIONAL)
11
7
HA-5340/883 (CLCC) TOP VIEW
NC S/H CNTL SUPPLY GND 1 2 14 9 +V 5 -V 13 SUPPLY GND 6
*
CHOLD 120pF -IN +IN CCOMP 15pF 7 OUT
+IN 3 OFFSET ADJ NC OFFSET ADJ NC 4 5 6 7
-IN 2
1 20 19 18 NC 17 NC 16 EXT. HOLD CAP. 15 NC 14 NC
S/H CONTROL
V- 8 9 10 11 12 13 SIG GND OUTPUT NC NC V+
NOTE: Buffer acts as a buffer in sample mode, acts as a closed switch in hold mode.
SIGNAL GND
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
7-8
Spec Number 511117-883 File Number 2452.1
Specifications HA5340/883
Absolute Maximum Ratings
Voltage Between V+ and V- Terminals . . . . . . . . . . . . . . . . . . . . 36V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24V Digital Input Voltage (S/H Pin) . . . . . . . . . . . . . . . . . . . . . . .+8V, -6V Output Current, Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20mA Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300oC ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <2000V
Thermal Information
Thermal Resistance JA JC CerDIP Package . . . . . . . . . . . . . . . . . 68oC/W 17oC/W Ceramic LCC Package . . . . . . . . . . . . 68oC/W 18oC/W Package Power Dissipation at +75oC CerDip Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5W Ceramic LCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5W Package Power Dissipation Derating Factor Above +75oC CerDip Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15mW/oC Ceramic LCC Package . . . . . . . . . . . . . . . . . . . . . . . . . 15mW/oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Temperature Range . . . . . . . . . . . . -55oC TA +125oC Operating Supply Voltage (VS) . . . . . . . . . . . . . . . . . . . . . . . . . . 15V Analog Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10V Logic Level Low (VIL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 0.8V Logic Level High (VIH) . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0V to 5.0V
TABLE 1. DC ELECTICAL PERFORMANCE CHARACTERISTICS Device Tested at: V+ = +15V; V- = -15V; VIL = 0.8V (Sample); VIH = 2.0V (Hold); CH = Internal = 135pF; Signal GND = Supply GND, Unless Otherwise Specified. GROUP A SUBGROUP 1 2, 3 Input Bias Current +IB 1 2, 3 -IB 1 2, 3 Input Offset Current IIO 1 2, 3 Open Loop Voltage Gain +AVS RL = 2k, CL = 60pF, VOUT = +10V RL = 2k, CL = 60pF, VOUT = -10V V+ = 5V, V- = -25V, VOUT = -10V, VS/H = -9.2V V+ = 25V, V- = -5V, VOUT = +10V, VS/H = 10.8V VOUT = +10V 1 2, 3 1 2, 3 1 2, 3 1 2, 3 1 2, 3 -IO VOUT = -10V 1 2, 3 Output Voltage Swing +VOP RL = 2k, CL = 60pF 1 2, 3 -VOP RL = 2k, CL = 60pF 1 2, 3 LIMITS TEMPERATURE +25oC +125oC, -55oC MIN -1.5 -3 -350 -350 -350 -350 -350 -350 110 100 110 100 72 72 72 72 10 10 -10 -10 10 10 MAX 1.5 3 350 350 350 350 350 350 -10 -10 UNITS mV mV nA nA nA nA nA nA dB dB dB dB dB dB dB dB mA mA mA mA V V V V
PARAMETERS Input Offset Voltage
SYMBOL VIO
CONDITIONS
+25oC +125oC, -55oC
+25oC +125oC, -55oC
+25oC +125oC, -55oC
+25oC +125oC, -55oC
-AVS
+25oC +125oC, -55oC
Common Mode Rejection Ratio
+CMRR
+25oC +125oC, -55oC
-CMRR
+25oC +125oC, -55oC
Output Current
+IO
+25oC +125oC, -55oC
+25oC +125oC, -55oC
+25oC +125oC, -55oC
+25oC +125oC, -55oC
CAUTION: These devices are sensitive to electronic discharge. Proper IC handling procedures should be followed.
Spec Number
511117-883
7-9
Specifications HA5340/883
TABLE 1. DC ELECTICAL PERFORMANCE CHARACTERISTICS (Continued) Device Tested at: V+ = +15V; V- = -15V; VIL = 0.8V (Sample); VIH = 2.0V (Hold); CH = Internal = 135pF; Signal GND = Supply GND, Unless Otherwise Specified. GROUP A SUBGROUP 1 2, 3 -ICC VOUT = 0V, IOUT = 0mA 1 2, 3 Power Supply Rejection Ratio +PSRR V+ = 13.5V, 16.5V V- = -15V, -15V V+ = +15V, +15V, V- = -13.5V, -16.5V VIN = 0V 1 2, 3 1 2, 3 1 2, 3 IINH VIN = 5V 1 2, 3 Digital Input Voltage VIL 1 2, 3 VIH 1 2, 3 Output Voltage Droop Rate VD VOUT = 0V 2 LIMITS TEMPERATURE +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +125oC MIN -25 -25 75 75 75 75 2.0 2.0 MAX 25 25 40 40 40 40 0.8 0.8 95 UNITS mA mA mA mA dB dB dB dB A A A A V V V V V/s
PARAMETERS Power Supply Current
SYMBOL +ICC
CONDITIONS VOUT = 0V, IOUT = 0mA
-PSRR
Digital Input Current
IINL
TABLE 2. AC ELECTICAL PERFORMANCE CHARACTERISTICS Device Tested at: V+ = +15V; V- = -15V; VIL = 0.8V (Sample); VIH = 2.0V (Hold); CH = Internal = 135pF; - Input Tied to Output, Signal GND = Supply GND, Unless Otherwise Specified. GROUP A SUBGROUP 4 4 5, 6 4 LIMITS TEMPERATURE +25oC +25oC +125oC, -55oC MIN -50 MAX 50 50 50 50 UNITS mV ns ns ns
PARAMETERS Hold Step Error Rise Time & Fall Time
SYMBOL VERROR TR
CONDITIONS VIL = 0V, VIH = 4.0V, tRISE(VS/H) = 15ns CL=60pF, RL=2k, AV = +1, VOUT = 0V to +200mV Step 10%, 90%pts CL = 60pF, RL = 2k, AV = +1, VOUT = 0V to -200mV Step 10%, 90%pts CL = 60pF, RL = 2k, AV = +1, VOUT = 0V to +200mV Step CL = 60pF, RL = 2k, AV = +1, VOUT = 0V to -200mV Step CL = 60pF, RL = 2k, AV = +1, VOUT = 0V to +10V Step, 25%, 75% pts CL = 60pF, RL = 2k, AV = +1, VOUT = 0V to -10V Step, 25%, 75% pts
TF
+25oC
Overshoot
+OS
4 5, 6 4 5, 6 4 5, 6 4 5, 6
+25oC +125oC, -55oC
40 40 40 40
60 60 60 60 -
% % % % V/s V/s V/s V/s
-OS
+25oC +125oC, -55oC
Slew Rate
+SR
+25oC +125oC, -55oC
-SR
+25oC +125oC, -55oC
CAUTION: These devices are sensitive to electronic discharge. Proper IC handling procedures should be followed.
Spec Number
511117-883
7-10
Specifications HA5340/883
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Hold Mode Feedthrough Sample Mode Noise Voltage Hold Mode Noise Voltage Input Capacitance Input Resistance 0.1% Acquisition Time SYMBOL VHMF En(SAMPLE) CONDITIONS VIN = 20VP-P , 200kHz DC to 10MHz, VS/H = 0V, RLOAD = 2K DC to 10MHz, VS/H = 5V, RLOAD = 2K VS/H = 0V VS/H = 0V, Delta VIN = 20V CL = 60pF, RL = 2K, VOUT = 0V to 10V Step FS = 450kHz, VIN = 20VP-P , 200kHz FS = 450kHz, VIN = 5VP-P , 500kHz VIN = 20VP-P , 200kHz VIN = 5VP-P , 500kHz NOTES 1 1 TEMPERATURE +25oC +25oC MIN MAX -70 335 UNITS dB VRMS VRMS
En(HOLD)
1
+25oC
-
100
CIN RIN TACQ 0.1%
1 1 1
+25oC +25oC +25oC
1 -
5 600
pF M ns
Total Harmonic Distortion Hold Mode
THD200K(HOLD)
1
+25oC
-
-50
dBc
THD500K(HOLD)
1
+25oC
-
-47
dBc
Total Harmonic Distortion Sample Mode
THD200K(SAMPLE) THD500K(SAMPLE)
1 1
+25oC +25oC
-
-60 -49
dBc dBc
NOTE: 1. The parameters listed in this table are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design release and upon design changes which would affect these characteristics.
TABLE 4. ELECTRICAL TEST REQUIREMENTS MIL-STD-883 TEST REQUIREMENTS Interim Electrical Parameters (Pre Burn-In) Final Electrical Test Parameters Group A Test Requirements Groups C and D Endpoints NOTE: 1. PDA applies to Subgroup 1 only. No other subgroups are included in PDA. SUBGROUPS (SEE TABLES 1 AND 2) 1(Note 1), 2, 3, 4, 5, 6 1, 2, 3, 4, 5, 6 1
CAUTION: These devices are sensitive to electronic discharge. Proper IC handling procedures should be followed.
Spec Number
511117-883
7-11
HA-5340/883 Die Characteristics
DIE DIMENSIONS: 84 x 139 x 19mils METALLIZATION: Type: Al, 1% Cu Thickness: 16kA 2kA GLASSIVATION: Type: Nitride (Si3N4) over Silox (SiO2, 5% Phos) Silox Thickness: 12kA 2.0kA Nitride Thickness: 3.5kA 1.5kA DIE ATTACH: Material: Gold Silicon Eutectic Alloy Temperature:Ceramic DIP - 460oC (Max) Ceramic LCC - 420oC (Max) WORST CASE CURRENT DENSITY: 5.33 x 104 A/cm2
Metallization Mask Layout
HA-5340/883
SUPPLY (13) GND S/H (14) CONTROL -IN (1) (9) +VSUPPLY (7) OUTPUT (7) OUTPUT
+IN (2) (6) SIG GND
OFFSET ADJ (3)
OFFSET ADJ (4)
(11) EXTERNAL HOLD CAP
-VSUPPLY (5)
Spec Number 7-12
511117-883
HA-5340/883 Burn-In Circuits
HA-5340/883 DIP BURN-IN/LIFE TEST CIRCUIT
1 2 R1 3 4 -15V D2 C2 5 6 7
14 13 12 11 10 9 8 C1 D1 +15V
HA-5340/883 LCC BURN-IN/LIFE TEST CIRCUIT
R1
3 4 5 6 7 -15V D2 C2 8 9
2
1
20
19 18 17 16 15 14
10
11
12
13 +15V C1 D1
NOTES: 1. R1 = 100k, 5%, 1/4W or 1/2W (per socket). 2. C1, C2 = 0.01F minimum per socket or 0.1F minimum per row. 3. D1, D2 = 1N4002 or equivalent (per board).
Spec Number 7-13
511117-883
HA-5340/883 Packaging
14 PIN CERAMIC DIP
LEAD MATERIAL: Type B LEAD FINISH: Type A PACKAGE MATERIAL: Ceramic, 90% Alumina PACKAGE SEAL: Material: Glass Frit Temperature: 450oC 10oC Method: Furnace Seal
INTERNAL LEAD WIRE: Material: Aluminum Diameter: 1.25 Mil Bonding Method: Ultrasonic COMPLIANT OUTLINE: 38510-D-1
20 PIN CERAMIC LCC
LEAD MATERIAL: Type C LEAD FINISH: Type A PACKAGE MATERIAL: Multilayer Ceramic, 90% Alumina PACKAGE SEAL: Material: Gold/Tin (80/20) Temperature: 320oC 10oC Method: Furnace Seal
Min , Dimensions are in inches. Max
INTERNAL LEAD WIRE: Material: Aluminum Diameter: 1.25 Mil Bonding Method: Ultrasonic COMPLIANT OUTLINE: 38510-C-2
NOTE:
All Dimensions are
Spec Number 7-14
511117-883
Semiconductor
HA5340
High Speed, Low Distortion, Precision Monolithic Sample and Hold Amplifier
errors. Teflon(R), polystyrene and polypropylene dielectric capacitor types offer good performance over the specified operating temperature range. The hold capacitor terminal (pin 11) remains at virtual ground potential. Any PC connection to this terminal should be kept short and ``guarded'' by the ground plane, since nearby signal lines or power supply voltages will introduce errors due to drift current.
(R)Teflon is a registered Trademark of Dupont Corporation.
DESIGN INFORMATION
August 1999
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied.
Applying the HA-5340
The HA-5340 has the uncommitted differential inputs of an op amp, allowing the Sample and Hold function to be combined with many conventional op amp circuits. See the Intersil Application Note 517 for a collection of circuit ideas. Layout A printed circuit board with ground plane is recommended for best performance. Bypass capacitors (0.01 to 0.1F, ceramic) should be provided from each power supply terminal to the Supply Ground terminal on pin 13. The ideal ground connections are pin 6 (SIG. Ground) directly to the system Signal Ground, and pin 13 (Supply Ground) directly to the system Supply Common. Hold Capacitor The HA-5340 includes a 135pF MOS hold capacitor, sufficient for most high speed applications (the Electrical Specifications section is based on this internal capacitor). Additional capacitance may be added between pins 7 and 11. This external hold capacitance will reduce droop rate at the expense of acquisition time, and provide other trade-offs as shown in the Performance Curves. The hold capacitor CH should have high insulation resistance and low dielectric absorption, to minimize droop
Applications
Figure 1 shows the HA-5340 connected as a unity gain noninverting amplifier - its most widely used configuration. As an input device for a fast successive - approximation A/D converter, it offers very high throughput rate for a monolithic IC sample/hold amplifier. Also, the HA-5340's hold step error is adjustable to zero using the Offset Adjust potentiometer, to deliver a 12-bit accurate output from the converter. The HA-5340 output circuit does not include short circuit protection, and consequently its output impedance remains low at high frequencies. Thus, the step changes in load current which occur during an A/D conversion are absorbed at the S/H output with minimum voltage error. A momentary short circuit to ground is permissible, but the output is not designed to tolerate a short of indefinite duration.
-15V +15V OFFSET ADJUST 15mV 50K 3 4 1 VIN S/H CONTROL H S 2 14 CONVERT HA- 5340 13 6 5 9 R/C ANALOG COMMON DIGITAL OUTPUT 5 9 11 135pF 7 13 INPUT
CH HI-774
SYSTEM POWER GROUND
SYSTEM SIGNAL GROUND
FIGURE 1. TYPICAL HA-5340 CONNECTIONS; NONINVERTING UNITY GAIN MODE NOTE: Pin Numbers Refer to DIP Package Only.
Spec Number 7-15
511117-883
HA5340
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied.
Test Circuits
HOLD STEP ERROR AND DROOP RATE
1 2
-INPUT +INPUT
7 OUTPUT 8 11 HA-5340 (CH = 135pF = INTERNAL) N.C. N.C.
VO
S/H CONTROL INPUT
14 S/H CONTROL
HOLD STEP ERROR 1. Observe the ``hold step'' voltage Vp:
HOLD (4.0V) S/H CONTROL SAMPLE (0V)
DROOP RATE TEST 1. Observe the voltage ``droop'', VO/T:
S/H CONTROL HOLD (4.0V) SAMPLE (0V)
VO VO Vp T
VO
2. Measure the slope of the output during hold, VO /T. 3. Droop can be positive or negative - usually to one rail or the other not to GND.
HOLD MODE FEED THROUGH ATTENUATION
+V ANALOG MUX OR SWITCH 1 20Vp-p 200kHz SINE WAVE 2 AIN 14 -IN +IN S/H CONTROL SUPPLY GND 13 S/H CONTROL INPUT TO SUPPLY COMMON 11 N.C. OUT CH REF COM 6 TO SIGNAL GND 7 HA-5340 9 5 VOUT -V
VIN
Feedthrough in dB = 20 Log VOUT = Voltsp-p, Hold Mode, VIN = Voltsp-p.
VOUT where: VIN
Spec Number 7-16
511117-883
HA5340
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied.
Performance Curves
VS = 15V, TA = +25oC, Unless Otherwise Specified.
TACQ vs. ADDITIONAL CH
TACQ POS 0 TO +10 STEP
S/H CONTROL
S/H CONTROL
VOUT
VOUT
DROOP RATE vs. HOLD CAPACITOR SIZE
ACQUISITION TIME (0.01%) vs. HOLD CAPACITANCE
HOLD STEP ERROR vs. TRISE CH = Internal; Temperature +25oC
HOLD STEP ERROR vs. HOLD CAPACITANCE TRISE = 5ns; Temperature = +25oC
Spec Number 7-17
511117-883
HA5340
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied.
Performance Curves
(Continued) VS = 15V, TA = +25oC, Unless Otherwise Specified.
HOLD STEP ERROR vs. TEMPERATURE VIH = 4V, CH = Internal tr = 5ns, 10ns, 20ns
HOLD STEP ERROR vs. TEMPERATURE VIH = 4V, CH = 470pF
CLOSED LOOP PHASE/GAIN AV = +100, 15V and 12V Supplies*
CLOSED LOOP PHASE/GAIN AV = +100
* 15V and 12V supplies trace the same line within the width of the line, therefore only one line is shown.
Spec Number 7-18
511117-883
HA-5340
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied.
Typical Performance Characteristics
PARAMETER Input Voltage Range Offset Voltage Drift Gain Bandwidth Product (ChExt = 0pF) Gain Bandwidth Product (ChExt = 100pF) Av = +1, VO = 200mVpp, RL = 2K, CL = 60pF Av = +1, VO = 200mVpp, RL = 2K, CL = 60pF CONDITIONS TEMPERATURE Full Full +25oC +25oC +25oC +25oC +25oC VO = 10V Step, RL = 2K, CL = 60pF VO = 10V Step, RL = 2K, CL = 60pF +25oC +25oC +25oC +25oC +25oC TYP 10 30 10 9.6 6.7 900 0.05 430 700 -15 0.2 200 UNITS V V/C MHz MHz MHz KHz ns ns ns ns ns
Gain Bandwidth Product (ChExt = 1000pF) Av = +1, VO = 200mVpp, RL = 2K, CL = 60pF Full Power Bandwidth Output Resistance (Hold Mode) 0.1% Acquisition Time 0.01% Acquisition Time Effective Aperture Delay Time Aperture Uncertainty 1mV Hold Mode Settling Time VO = 20Vpp, RL = 2K, CL = 60pF, Slew Rate Limited
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Spec Number 7-19
511117-883

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